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d a t a sh eet preliminary speci?cation supersedes data of 1998 oct 22 file under integrated circuits, ic02 2000 may 08 integrated circuits tda933xh series i 2 c-bus controlled tv display processors
2000 may 08 2 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series features available in all ics: can be used in both single scan (50 or 60 hz) and double scan (100 or 120 hz) applications yuv input and linear rgb input with fast blanking separate osd/text input with fast blanking or blending black stretching of non-standard luminance signals switchable matrix for the colour difference signals rgb control circuit with continuous cathode calibration (ccc), plus white point and black level offset adjustment blue stretch circuit which offsets colours near white towards blue internal clock generation for the deflection processing, which is synchronized by a 12 mhz ceramic resonator oscillator horizontal synchronization with two control loops and alignment-free horizontal oscillator slow start and slow stop of the horizontal drive pulses low-power start-up option for the horizontal drive circuit vertical count-down circuit vertical driver optimized for dc-coupled vertical output stages vertical and horizontal geometry processing horizontal and vertical zoom possibility and vertical scroll function for application with 16 : 9 picture tubes horizontal parallelogram and bow correction i 2 c-bus control of various functions low dissipation. general description the tda933xh series are display processors for high-end television receivers which contain the following functions: rgb control processor with y, u and v inputs, a linear rgb input for scart or vga signals with fast blanking, a linear rgb input for osd and text signals with a fast blanking or blending option and an rgb output stage with black current stabilization, which is realized with the ccc (2-point black current measurement) system. programmable deflection processor with internal clock generation, which generates the drive signals for the horizontal, east-west (e-w) and vertical deflection. the circuit has various features that are attractive for the application of 16 : 9 picture tubes. the circuit can be used in both single scan (50 or 60 hz) and double scan (100 or 120 hz) applications. in addition to these functions, the tda9331h and tda9332h have a multi-sync function for the horizontal pll, with a frequency range from 30 to 50 khz (2f h mode) or 15 to 25 khz (1f h mode), so that the ics can also be used to display svga signals. the supply voltage of the ics is 8 v. they are each contained in a 44-pin qfp package. ordering information type number package name description version TDA9330h qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 tda9331h tda9332h
2000 may 08 3 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series survey of ic types quick reference data ic version vga mode dac output TDA9330h no i 2 c-bus controlled tda9331h yes proportional to vga frequency tda9332h yes i 2 c-bus controlled symbol parameter min. typ. max. unit supply v p supply voltage - 8.0 - v i p supply current (v p1 plus v p2 ) - 50 - ma input voltages v i(y)(b-w) luminance input signal (black-to-white value) - 1.0/0.315 - v v i(u)(p-p) u input signal (peak-to-peak value) - 1.33 - v v i(v)(p-p) v input signal (peak-to-peak value) - 1.05 - v v i(rgb)(b-w) rgb input signal (black-to-white value) - 0.7 - v v i(hsync) horizontal sync input (h d ) - ttl - v v i(vsync) vertical sync input (v d ) - ttl - v v i(iic) i 2 c-bus inputs (sda and scl) - cmos 5 v - v output signals v o(rgb)(b-w) rgb output signal amplitude (black-to-white value) - 2.0 - v i o(hor) horizontal output current -- 10 ma i o(ver)(p-p) vertical output current (peak-to-peak value) - 0.95 - ma i o(ew) e-w drive output current -- 1.2 ma
2000 may 08 4 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series block diagram handbook, full pagewidth mgr445 switch y y u v sat contr u v saturation control colour difference matrix r g b contrast control r g b rgb insertion r gg b bri white point white point and brightness control r b output amplifier and buffer blue stretch 40 41 42 28 27 26 yin uin vin rgb-yuv matrix black stretch pwl and beam current limiter continuous cathode calibration 44 30 31 32 ri1 gi1 bi1 supply h-shift soft start/stop low-power start-up h/v divider 19 6-bit dacs 2 4-bit dacs i 2 c-bus transceiver 10 43 11 25 18 6 19 17 7 39 dec bg gnd1 gnd2 23 v p1 dec vd v p2 clock generation and 1st loop 20 21 13 14 22 phase-2 loop horizontal output 15 16 vsc i ref ramp generator 1 24 vertical geometry 3 e-w geometry geometry control 24 12 hsel 33 29 38 37 36 35 34 tda933xh bl1 fbcso bl2 gi2 ri2 pwl bi2 bcl bo go ro blkin dacout sda scl vdoa 58 9 vdob ewo ehtin xtali xtalo lpsu flash hout sco hfb dpc h d v d fig.1 block diagram. this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ...
2000 may 08 5 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series pinning symbol pin description vdoa 1 vertical drive output a vdob 2 vertical drive output b ewo 3 e-w output ehtin 4 eht compensation input flash 5 ?ash detection input gnd1 6 ground 1 dec vd 7 digital supply decoupling hout 8 horizontal output sco 9 sandcastle pulse output scl 10 serial clock input sda 11 serial data input/output hsel 12 selection of horizontal frequency hfb 13 horizontal ?yback pulse input dpc 14 dynamic phase compensation vsc 15 vertical sawtooth capacitor i ref 16 reference current input v p1 17 positive supply 1 (+8 v) dec bg 18 band gap decoupling gnd2 19 ground 2 xtali 20 crystal input xtalo 21 crystal output lpsu 22 low-power start-up supply v d 23 vertical sync input h d 24 horizontal sync input dacout 25 dac output vin 26 v-signal input uin 27 u-signal input yin 28 luminance input fbcso 29 ?xed beam current switch-off input ri1 30 red 1 input for insertion gi1 31 green 1 input for insertion bi1 32 blue 1 input for insertion bl1 33 fast blanking input for rgb-1 pwl 34 peak white limiting decoupling ri2 35 red 2 input for insertion gi2 36 green 2 input for insertion bi2 37 blue 2 input for insertion bl2 38 fast blanking/blending input for rgb-2 v p2 39 positive supply 2 (+8 v) ro 40 red output
2000 may 08 6 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series go 41 green output bo 42 blue output bcl 43 beam current limiting input blkin 44 black current input symbol pin description handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 tda933xh mgr446 bl1 bi1 gi1 ri1 yin uin vin dacout h d v d vdoa vdob ewo ehtin flash gnd1 hout sco sda fbcso bcl bo go ro v p2 bl2 gi2 ri2 pwl blkin bi2 hfb dpc vsc i ref v p1 dec bg xtali xtalo lpsu hsel gnd2 dec vd scl fig.2 pin configuration.
2000 may 08 7 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series functional description rgb control circuit i nput signals the rgb control circuit of the tda933xh contains three sets of input signals: yuv input signals, which are supplied by the input processor or the feature box. bit gai can be used to switch the luminance input signal sensitivity between 0.45 v (p-p) and 1.0 v (b-w). the nominal input signals for u and v are 1.33 v (p-p) and 1.05 v (p-p), respectively. these input signals are controlled on contrast, saturation and brightness. the first rgb input is intended for external signals (scart in 1f h and vga in 2f h applications), which have an amplitude of 0.7 v (p-p) typical. this input is also controlled on contrast, saturation and brightness. the second rgb input is intended for osd and teletext signals. the required input signals have an amplitude of 0.7 v (p-p). the switching between the internal signal and the osd signal can be realized via a blending function or via fast blanking. this input is only controlled on brightness. switching between the various sources can be realized via the i 2 c-bus and by fast insertion switches. the fast insertion switches can be enabled via the i 2 c-bus. the circuit contains switchable matrix circuits for the colour difference signals so that the colour reproduction can be adapted for pal/secam and ntsc. for ntsc, two different matrices can be chosen. in addition, a matrix for high-definition atsc signals is available. o utput amplifier the output signal has an amplitude of approximately 2 v (b-w) at nominal input signals and nominal settings of the controls. the required white point setting of the picture tube can be realized by means of three separate gain settings for the rgb channels. to obtain an accurate biasing of the picture tube, a ccc circuit has been developed. this function is realized by a 2-point black level stabilization circuit. by inserting two test levels for each gun and comparing the resulting cathode currents with two different reference currents, the influence of the picture tube parameters such as the spread in cut-off voltage can be eliminated. this 2-point stabilization is based on the principle that the ratio between the cathode currents is coupled to the ratio between the drive voltages according to: the feedback loop makes the ratio between cathode currents i k1 and i k2 equal to the ratio between the reference currents (which are internally fixed) by changing the (black) level and the amplitude of the rgb output signals via two converging loops. the system operates in such a way that the black level of the drive signal is controlled to the cut-off point of the gun. in this way, a very good grey scale tracking is obtained. the accuracy of the adjustment of the black level is only dependent on the ratio of internal currents and these can be made very accurately in integrated circuits. an additional advantage of the 2-point measurement is that the control system makes the absolute value of i k1 and i k2 identical to the internal reference currents. because this adjustment is obtained by adapting the gain of the rgb control stage, this control stabilizes the gain of the complete channel (rgb output stage and cathode characteristic). as a result, this 2-point loop compensates for variations in the gain figures during life. an important property of the 2-point stabilization is that the offset and the gain of the rgb path are adjusted by the feedback loop. hence, the maximum drive voltage for the cathode is fixed by the relationship between the test pulses, the reference current and the relative gain setting of the three channels. consequently, the drive level of the crt cannot be adjusted by adapting the gain of the rgb output stage. because different picture tubes may require different drive levels, the typical cathode drive level amplitude can be adjusted by means of an i 2 c-bus setting. depending on the selected cathode drive level, the typical gain of the rgb output stages can be fixed, taking into account the drive capability of the rgb outputs (pins 40 to 42). more details about the design are given in the application report (see also chapter characteristics; note 11). the measurement of the high and the low currents of the 2-point stabilization circuit is performed in two consecutive fields. the leakage current is measured in each field. the maximum allowable leakage current is 100 m a. for extra flexibility, it also possible to switch the ccc circuit to 1-point stabilization with the opc bit. in this mode, only the black level at the rgb outputs is controlled by the loop. the cathode drive level setting has no influence on the gain in this mode. this level should be set to the nominal value to get the correct amplitude of the measuring pulses. i k1 i k2 ------ - v dr1 v dr1 ---------- - ? ?? g =
2000 may 08 8 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series via the i 2 c-bus, an adjustable offset can be made on the black level of red and green channels with respect to the level that is generated by the black current control loop. these controls can be used to adjust the colour temperature of the dark part of the picture, independent of the white point adjustment. when the tv receiver is switched on, the black current stabilization circuit is directly activated and the rgb outputs are blanked. the blanking is switched off as soon as the loop has stabilized (e.g. the first time that bit bcf changes from 1 to 0, see also chapter characteristics; note 15). this ensures that the switch-on time is reduced to a minimum and is only dependent on the warm-up time of the picture tube. the black current stabilization system checks the output level of the three channels and indicates whether the black level of the lowest rgb output of the ic is in a certain window (wbc bit), below or above this window (hbc bit). this indication can be read from the i 2 c-bus and can be used for automatic adjustment of voltage v g2 during the production of the tv receiver. when a failure occurs in the black current loop (e.g. due to an open circuit), status bit bcf is set. this information can be used to blank the picture tube to avoid damage to the screen. the control circuit contains an average beam current limiting circuit and a peak white level (pwl) circuit. the pwl detects small white areas in the picture that are not detected by the average beam current limiter. the pwl can be adjusted via the i 2 c-bus. a low-pass filter is placed in front of the peak detector to prevent it from reacting to short transients in the video signal. the capacitor of the low-pass filter is connected externally so that the set maker can adapt the time constant as required. the ic also contains a soft clipper that limits the amplitude of the short transients in the rgb output signals. in this way, spot blooming on, for instance, subtitles is prevented. the difference between the pwl and the soft clipping level can be adjusted via the i 2 c-bus in a few steps. the vertical blanking is adapted to the vertical frequency of the incoming signal (50 or 100 hz or, 60 or 120 hz). when the flyback time of the vertical output stage is greater than the 60 hz blanking time, the blanking can be increased to the same value as that of the 50 hz blanking. this can be set by means of bit lbm. when no video is available, it is possible to insert a blue background. this feature can be activated via bit ebb. synchronization and de?ection processing h orizontal synchronization and drive circuit the horizontal drive signal is obtained from an internal vco which runs at a frequency of 440 times (2f h mode) or 880 times (1f h mode) the frequency of the incoming h d signal. the free-running frequency of this vco is calibrated by a crystal oscillator which needs an external 12 mhz crystal or ceramic resonator as a reference. it is also possible to supply an external reference signal to the ic (in this case, the external resonator should be removed). the vco is synchronized to the incoming horizontal h d pulse (applied from the feature box or the input processor) by a pll with an internal time constant. the frequency of the horizontal drive signal (1f h or 2f h ) is selected by means of a switching pin, which must be connected to ground or left open circuit. for hdtv applications, it is possible to change the free-running frequency of the horizontal drive output from 31.2 khz to 33.7 khz by means of bit hdtv. for safety reasons, switching between 1f h and 2f h modes is only possible when the ic is in the standby mode. for the tda9331h and tda9332h, it is also possible to set the horizontal pll to a multi-sync mode by means of bit vga. in this mode, the circuit detects the frequency of the incoming sync pulses and adjusts the centre frequency of the vco accordingly by means of an internal digital-to-analog-converter (dac). the frequency range in this mode is 30 to 50 khz at the output. the polarities of the incoming h d and v d pulses are detected internally. the detected polarity can be read out via status bits hpol and vpol. the horizontal drive signal is generated by a second control loop which compares the phase of the reference signal (applied from the internal vco) with the flyback pulse. the time constant of this loop is set internally. the ic has a dynamic horizontal phase correction input, which can be used to compensate phase shifts that are caused by beam current variations. additional settings of the horizontal deflection (which are realized via the second loop) are the horizontal shift and horizontal parallelogram and bow corrections (see chapter characteristics; fig.16). the adjustments are realized via the i 2 c-bus. when no horizontal flyback pulse is detected during three consecutive line periods, status bit nhf is set (output status byte 01-d3; see table 3).
2000 may 08 9 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series the horizontal drive signal is switched on and off via the so-called slow-start/slow-stop procedure. this function is realized by varying the t on of the horizontal drive pulse. for eht generators without a bleeder, the ic can be set to a fixed beam current mode via bit fbc. in this case, the picture tube capacitance is discharged with a current of approximately 1 ma. the magnitude of the discharge current is controlled via the black current feedback loop. if necessary, the discharge current can be enlarged with the aid of an external current division circuit. with the fixed beam current option activated, it is still possible to have a black screen during switch-off. this can be realized by placing the vertical deflection in an overscan position. this mode is activated via bit oso. an additional mode of the ic is the low-power start-up mode. this mode is activated when a supply voltage of 5 v is supplied to the start-up pin. the required current for this mode is 3 ma (typ.). in this condition, the horizontal drive signal has the nominal t off and the t on grows gradually from zero to approximately 30% of the nominal value. this results in a line frequency of approximately 50 khz (2f h ) or 25 khz (1f h ). the output signal remains unchanged until the main supply voltage is switched on and the i 2 c-bus data has been received. the horizontal drive then gradually changes to the nominal frequency and duty cycle via the slow-start procedure. the ic can only be switched on and to standby mode when both standby bits (stb0 and stb1) are changed. the circuit will not react when only one bit changes polarity. the ic has a general purpose bus controlled dac output with a 6-bit resolution and with an output voltage range between 0.2 to 4 v. in the tda9331h, the dc voltage on this output is proportional to the horizontal line frequency (only in vga mode). this voltage can be used to control the supply voltage of the horizontal deflection stage, to maintain constant picture width for higher line frequencies. v ertical deflection and geometry control the drive signals for the vertical and e-w deflection circuits are generated by a vertical divider, which derives its clock signal from the line oscillator. the divider is synchronized by the incoming v d pulse, generated by the input processor or the feature box. the vertical ramp generator requires an external resistor and capacitor; the tolerances for these components must be small. in the normal mode, the vertical deflection operates in constant slope and adapts its amplitude, depending on the frequency of the incoming signal (50 or 60 hz, or 100 or 120 hz). when the tda933xh is switched to the vga mode, the amplitude of the vertical scan is stabilized and independent of the incoming vertical frequency. in this mode, the e-w drive amplitude is proportional to the horizontal frequency so that the correction on the screen is not affected. the vertical drive is realized by a differential output current. the outputs must be dc-coupled to the vertical output stage (e.g. tda8354). the vertical geometry can be adjusted via the i 2 c-bus. controls are possible for the following parameters: vertical amplitude s-correction vertical slope vertical shift (only for compensation of offsets in output stage or picture tube) vertical zoom vertical scroll (shifting the picture in the vertical direction when the vertical scan is expanded) vertical wait, an adjustable delay for the start of the vertical scan. with regard to the vertical wait, the following conditions are valid: in the 1f h tv mode, the start of the vertical scan is fixed and cannot be adjusted with the vertical wait in the 2f h tv mode, the start of the vertical scan depends on the value of the vertical scan reference (vsr) bus bit. if vsr = 0, the start of the vertical scan is related to the end of the incoming v d pulse. if vsr = 1, it is related to the start. in both cases, the start of the scan can be adjusted with the vertical wait setting in the multi-sync mode (tda9331h and tda9332h both in 1f h mode and 2f h mode), the start of the vertical scan is related to the start of the incoming v d pulse and can be adjusted with the vertical wait setting. the minimum value for the vertical wait setting is 8 line periods. if the setting is lower than 8, the wait period will remain at 8 line periods. the e-w drive circuit has a single-ended output. the e-w geometry can be adjusted on the following parameters: horizontal width with increased range because of the zoom feature e-w parabola/width ratio e-w upper corner/parabola ratio e-w lower corner/parabola ratio e-w trapezium.
2000 may 08 10 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series the ic has an eht compensation input which controls both the vertical and the e-w output signals. the relative control effect on both outputs can be adjusted via the i 2 c-bus (sensitivity of vertical correction is fixed; e-w correction variable). to avoid damage to the picture tube in the event of missing or malfunctioning vertical deflection, a vertical guard function is available at the sandcastle pin (pin sco). the vertical guard pulse from the vertical output stage (tda835x) should be connected to the sandcastle pin, which acts as a current sense input. if the guard pulse is missing or lasts too long, bit ndf is set in the status register and the rgb outputs are blanked. if the guard function is disabled via bit evg, only ndf status bit nhf is set. the ic also has inputs for flash and overvoltage protection. more details about these functions are given in chapter characteristics; note 43. i 2 c-bus specification the slave address of the ic is given in table 1. the circuit operates up to clock frequencies of 400 khz. valid subaddresses: 00 to 1f, subaddress fe is reserved for test purposes. the auto-increment mode is available for subaddresses. table 1 slave address (8c) a6 a5 a4 a3 a2 a1 a0 r/w 10001101/0
2000 may 08 11 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series table 2 input control bits notes 1. for zero parallelogram and bow correction use register value 7 dec. 2. see chapter characteristics; note 47. 3. bit vga is not available in the TDA9330h. function subaddress (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0 rgb processing-1 00 mat ebb sbl rbl bls bks ie1 ie2 rgb processing-2 01 mus fbc obl akb cl3 cl2 cl1 cl0 wide horizontal blanking 02 hbl tfbc gai stb0 hb3 hb2 hb1 hb0 horizontal de?ection 03 hdtv vsr 0 stb1 poc prd vga (3) ess vertical de?ection 04 opc vff lbm dip oso svf evg dl brightness 05 0 0 a5 a4 a3 a2 a1 a0 saturation 06 0 0 a5 a4 a3 a2 a1 a0 contrast 07 0 0 a5 a4 a3 a2 a1 a0 white point r 08 0 0 a5 a4 a3 a2 a1 a0 white point g 09 0 0 a5 a4 a3 a2 a1 a0 white point b 0a 0 0 a5 a4 a3 a2 a1 a0 peak white limiting 0b 0 0 sc1 sc0 a3 a2 a1 a0 horizontal shift 0c 0 0 a5 a4 a3 a2 a1 a0 horizontal parallelogram (1) 0d 0000a3a2a1a0 e-w width 0e 0 0 a5 a4 a3 a2 a1 a0 e-w parabola/width 0f 0 0 a5 a4 a3 a2 a1 a0 e-w upper corner/parabola 10 0 0 a5 a4 a3 a2 a1 a0 e-w trapezium 11 0 0 a5 a4 a3 a2 a1 a0 e-w eht compensation sensitivity 12 0 0 a5 a4 a3 a2 a1 a0 vertical slope 13 0 0 a5 a4 a3 a2 a1 a0 vertical amplitude 14 0 0 a5 a4 a3 a2 a1 a0 s-correction 15 0 0 a5 a4 a3 a2 a1 a0 vertical shift 16 0 0 a5 a4 a3 a2 a1 a0 vertical zoom 17 0 0 a5 a4 a3 a2 a1 a0 vertical scroll 18 0 0 a5 a4 a3 a2 a1 a0 vertical wait 19 0 0 0 a4 a3 a2 a1 a0 dac output (2) 1a 0 0 a5 a4 a3 a2 a1 a0 black level offset r 1b 0000a3a2a1a0 black level offset g 1c 0000a3a2a1a0 horizontal timing 1d 0 0 0 hdcl lbl3 lbl2 lbl1 lbl0 e-w lower corner/parabola 1e 0 0 a5 a4 a3 a2 a1 a0 horizontal bow (1) 1f 0000a3a2a1a0
2000 may 08 12 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series table 3 output status bits function subaddress (hex) data byte d7 d6 d5 d4 d3 d2 d1 d0 output status bytes 00 por fsi sl xpr ndf in1 in2 wbc 01 n2 id2 id1 id0 nhf bcf fls nrf 02 x x x x x hpol vpol hbc input control bits table 4 colour difference matrix table 5 enable blue-back table 6 service blanking table 7 rgb blanking table 8 blue stretch table 9 black stretch table 10 enable fast blanking rgb-1 table 11 enable fast blanking rgb-2 table 12 fixed beam current switch-off table 13 blending function on osd; note 1 note 1. when bit obl is set to 1, the blending function is always activated, independent of the setting of bit ie2. table 14 black current stabilization mat mus matrix position 00 pal 0 1 atsc 1 0 ntsc japan 1 1 ntsc usa ebb mode 0 blue-black switched off 1 blue-black switched on sbl service blanking mode 0 off 1on rbl rgb blanking 0 not active 1 active bls blue stretch mode 0 off 1on bks black stretch mode 0 off 1on ie1 fast blanking 0 not active 1 active ie2 fast blanking 0 not active 1 active fbc mode 0 switch-off with blanked rgb outputs 1 switch-off with ?xed beam current obl mode 0 osd via fast blanking 1 osd via blending function akb opc mode 0 0 2-point control 0 1 1-point control 1 - not active
2000 may 08 13 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series table 15 cathode drive level (15 steps; 3.6 v/step) note 1. the given values are valid for the following conditions: a) nominal cvbs input signal. b) settings for contrast and white point nominal. c) black and blue stretch switched off. d) gain of output stage such that no clipping occurs. e) beam current limiting not active. f) gamma of picture tube is 2.25. g) the tolerance on these values is approximately 3v. table 16 rgb blanking mode table 17 picture tube discharge time note 1. see chapter characteristics; fig.15 table 18 gain of luminance channel table 19 standby table 20 position of wide blanking (14 steps; 1f h mode 0.29 m s/step; 2f h mode 0.145 m s/step) note 1. see chapter characteristics; note 13. table 21 horizontal free-running frequency in tv mode table 22 vertical scan reference in 2f h tv mode table 23 synchronization mode table 24 overvoltage input mode table 25 multi-sync mode table 26 extended slow start mode cl3 cl2 cl1 cl0 setting of cathode drive amplitude (1) 0000 41v (b-w) 1000 70v (b-w) 1111 95v (b-w) hbl mode 0 normal blanking (horizontal ?yback) 1 wide blanking tfbc mode 0 18.6 ms 1 25 ms gai mode 0 normal gain [v 28 = 1 v (b-w)] 1 high gain [v 28 = 0.45 v (p-p)] stb0 stb1 condition 0 0 horizontal drive off 0 1 no action 1 0 no action 1 1 horizontal drive on hb3 hb2 hb1 hb0 timing of blanking (1) 1f h mode 2f h mode 0000 - 2.03 m s - 1.015 m s 0111 0 m s0 m s 111 - 2.03 m s 1.015 m s hdtv frequency 1f h mode 2f h mode 0 15.65 khz 31.3 khz 1 16.85 khz 33.7 khz vsr vertical scan reference 0 end of v d pulse 1 start of v d pulse poc mode 0 synchronization active 1 synchronization not active prd overvoltage mode 0 detection mode 1 protection mode vga mode 0 horizontal frequency ?xed by internal reference 1 multi-sync function switched on ess extended slow start mode 0 not active 1 active
2000 may 08 14 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series table 27 long blanking mode table 28 vertical free-running frequency in tv mode table 29 de-interlace phase table 30 switch-off in vertical overscan table 31 select vertical frequency table 32 enable vertical guard (rgb blanking) table 33 interlace table 34 soft clipping level table 35 clamp pulse timing note 1. see chapter characteristics; note 13. table 36 start line blanking (15 steps; 2 line locked clock period per step; 1 line period is 440 llc pulses) note 1. see chapter characteristics; note 13. output status bits table 37 power-on reset table 38 field frequency indication table 39 phase 1 ( j 1 ) lock indication lbm blanking mode 0 adapted to standard (50 or 60 hz) 1 ?xed in accordance with 50 hz standard vff frequency 0 50 hz (svf = 0) or 100 hz (svf = 1) 1 60 hz (svf = 0) or 120 hz (svf = 1) dip phase 0 delay of 1st ?eld (start of synchronized v d pulse coincides with h-?yback) with 0.5 h 1 delay of 2nd ?eld with 0.5 h oso mode 0 switch-off unde?ned 1 switch-off in vertical overscan svf mode 0 vertical frequency is 50 or 60 hz 1 vertical frequency is 100 or 120 hz evg vertical guard mode 0 not active 1 active dl status 0 interlace 1 de-interlace sc1 sc0 voltage difference between soft clipping and pwl 0 0 0% above pwl 0 1 5% above pwl 1 0 10% above pwl 1 1 soft clipping off hdcl mode (1) 0 normal timing 1 hdtv timing lbl3 lbl2 lbl1 lbl0 start line blanking (1) 0000 +14 llc 0111 normal 1111 - 16 llc por mode 0 normal 1 power-down fsi frequency 0 50 or 100 hz 1 60 or 120 hz sl indication 0 not locked 1 locked
2000 may 08 15 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series table 40 x-ray protection table 41 output of vertical guard table 42 indication of rgb-1 insertion table 43 indication of rgb-2 insertion table 44 indication of output black level inside/outside v g2 alignment window note 1. see chapter characteristics; note 16. table 45 ic identi?cation table 46 mask version indication table 47 condition of horizontal ?yback table 48 indication of failure in black current circuit table 49 indication of ?ash detection table 50 locking of reference oscillator to crystal oscillator table 51 indication of output black level below or above the middle of v g2 alignment window note 1. see chapter characteristics; note 16. table 52 polarity of h d input pulse table 53 polarity of v d input pulse xpr overvoltage 0 no overvoltage detected 1 overvoltage detected ndf vertical output stage 0ok 1 failure in1 rgb insertion 0no 1yes in2 rgb insertion 0no 1yes wbc condition (1) 0 black current stabilization outside window 1 black current stabilization inside window id2 id1 id0 ic version 0 0 0 TDA9330h 0 0 1 tda9332h 0 1 1 tda9331h n2 mask version 0 n1 version 1 n2 version nhf condition 0 ?yback pulse present 1 ?yback pulse not present bcf condition 0 normal operation 1 failure in black current stabilization circuit fls condition 0 no ?ash-over detected 1 ?ash-over detected nrf condition 0 reference oscillator is locked 1 reference oscillator is not locked hbc condition (1) 0 black current stabilization below window 1 black current stabilization above window hpol polarity 0 positive 1 negative vpol polarity 0 positive 1 negative
2000 may 08 16 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series limiting values in accordance with the absolute maximum rating system (iec 60134). thermal characteristics symbol parameter conditions min. max. unit v p supply voltage - 9.0 v t stg storage temperature - 25 +150 c t amb ambient temperature 0 70 c t sol soldering temperature for 5 s - 260 c t j junction temperature - 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 60 k/w quality specification in accordance with snw-fq-611e-part e . esd protection all pins are protected against esd by internal protection diodes, and meet the following specification: human body model (r = 1.5 k w ; c = 100 pf): all pins > 3000 v machine model (r = 0 w ; c = 200 pf): all pins > 300 v. latch-up performance at an ambient temperature of 50 c all pins meet the following specification: positive stress test: i trigger 3 100 ma or v pin 3 1.5 v cc(max) negative stress test: i trigger - 100 ma or v pin - 0.5 v cc(max) . at an ambient temperature of 70 c, all pins meet the specification as mentioned above, with the exception of pin 32, which can withstand a negative stress current of at least 50 ma.
2000 may 08 17 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series characteristics v p =8v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies m ain supply ; pins 17 and 39 v p1 supply voltage 7.2 8.0 8.8 v v por power-on reset voltage level note 1 5.8 6.1 6.5 v i p1 supply current pin 17 plus pin 39 44 50 58 ma pin 17 - 22 - ma pin 39 - 28 - ma p tot total power dissipation - 400 - mw l ow - power start - up ; pin 22 v p2 supply voltage note 2 4.5 5.0 5.5 v i p2 supply current - 3.0 4.5 ma rgb control circuit l uminance input ; pin 28 v i(y)(b-w) luminance input voltage (black-to-white value) gai = 0 - 1.0 1.5 v z i input impedance 10 -- m w c i input capacitance -- 5pf i i(y)(clamp) input current during clamping - 25 0 +25 m a u/v inputs ; pins 27 and 26 v i(u)(p-p) u input signal amplitude (peak-to-peak value) - 1.33 2.0 v v i(v)(p-p) v input signal amplitude (peak-to-peak value) - 1.05 1.6 v z i input impedance 10 -- m w c i input capacitance -- 5pf i i(uv)(clamp) input current during clamping - 20 0 +25 m a rgb-1 input (scart/vga); pins 30 to 32; note 3 v i(b-w) input signal amplitude (black-to-white value) - 0.7 1.0 v d v o difference between black level of yuv and rgb-1 signals at the outputs -- 10 mv z i input impedance 10 -- m w c i input capacitance -- 5pf i i(clamp) input current during clamping - 25 0 +25 m a d t d delay difference for the three channels note 5 - 0 - ns
2000 may 08 18 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series f ast blanking input (rgb-1); pin 33 v i(bl1) input voltage no data insertion 0 - 0.45 v data insertion 0.9 - 3.0 v d t d delay difference between insertion to rgb out and rgb in to rgb out data insertion; note 5 - 10 20 ns i i(bl1) input current source current; note 6 -- 0.12 - 0.2 ma ss int suppression of internal rgb signals insertion; f i = 0 to 10 mhz; notes 5 and 7 50 55 - db ss ext suppression of external rgb signals no insertion; f i = 0 to 10 mhz; notes 5 and 7 50 55 - db rgb-2 input (osd/text); pins 35 to 37 v i(b-w) input signal amplitude (black-to-white value) - 0.7 1.0 v d v o difference between black level of yuv/rgb-1 and rgb-2 signals at the outputs -- tbf mv z i input impedance 10 -- m w c i input capacitance -- 5pf i i(clamp) input current during clamping - 40 0 +40 m a d t d delay difference for the three channels note 5 - 0 - ns b lending ( fast blanking ) input (rgb-2); pin 38; note 8 blending function (obl = 1) v i(bl2)(1) input voltage no data insertion 0 - 0.05 v 50% insertion 0.69 0.725 0.76 v 100% insertion 1.42 1.47 3.0 v active blending range 0.31 - 1.14 v ins (osd) percentage of data insertion v i = 0.31 v 0 1 4 % v i = 0.725 v 45 50 55 % v i = 1.14 v 96 99 100 % internal signal is 50% 48 50 52 % v i(max) slope of blending curve 50% insertion - 160 - %/v fast blanking function (obl = 0) v i(bl2)(0) input voltage no data insertion 0 - 0.3 v data insertion 0.9 - 3.0 v symbol parameter conditions min. typ. max. unit
2000 may 08 19 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series general d t d delay difference between insertion to rgb out and rgb in to rgb out data insertion; note 5 - 20 26 ns i i(bl2) input current source current; note 6 -- 1 - 5 m a ss int suppression of internal rgb signals insertion; f i = 0 to 10 mhz; notes 5 and 7 50 55 - db ss ext suppression of external rgb signals no insertion; f i = 0 to 10 mhz; notes 5 and 7 50 55 - db c olour difference matrices ; note 3 pal/secam mode; the matrix results in the following signal g - yg - y - 0.51 (r - y) - 0.19 (b - y) atsc mode; the matrix results in the following signal; note 4 g - yg - y - 0.30 (r - y) - 0.10 (b - y) ntsc mode; the matrix results in the following modi?ed colour difference signals mus bit = 0 (japan) r - y(r - y)* 1.39 (r - y) - 0.07 (b - y) g - y(g - y)* - 0.46 (r - y) - 0.15 (b - y) b - y(b - y)* b - y mus bit = 1 (usa) r - y(r - y)* 1.32 (r - y) - 0.12 (b - y) g - y(g - y)* - 0.42 (r - y) - 0.25 (b - y) b - y(b - y)* - 0.03 (r - y) +1.08 (b - y) c ontrols saturation control; note 9 cr sat saturation control range small signal gain; 63 steps; see fig.5 0 - 300 % cr sat(nom) i 2 c-bus setting for nominal saturation yuv input signal - 20 dec - cr sat(min) minimum saturation i 2 c-bus setting 0 -- 50 - db contrast control; note 9 cr contr contrast control range 63 steps; see fig.6 - 18 - db tracking between the three channels over a control range of 10 db -- 0.5 db brightness control; note 9 cr bri brightness control range 63 steps; see fig.7 - 1.1 - v symbol parameter conditions min. typ. max. unit
2000 may 08 20 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series b lack level stretcher ; note 10 d v bl(max) maximum black level shift a-to-a; see fig.8 15 21 27 ire d v bl black level shift at 100% peak white - 10 + 1 ire at 50% peak white - 1 -+ 3 ire at 15% peak white 6 8 10 ire rgb amplifier outputs : pins 40 to 42 v 40-42(b-w) output signal amplitude (black-to-white value) at nominal luminance input signal and nominal contrast, cathode drive level and white-point adjustment; note 11 - 2.0 - v v o output voltage range 1 - v cc - 2v z o output impedance note 12 - 120 150 w i sink sink current emitter follower output - 2 - ma v o(red)(p-p) output signal amplitude for the red channel (peak-to-peak value) at nominal settings for contrast and saturation control and no luminance signal at the input (r - y, pal); note 11 - 2.1 - v v bl(nom) nominal black level voltage - 2.5 - v v bl black level voltage when black level stabilization is switched off (via akb bit) - 2.5 - v t w(blank) width of video blanking pulse with bit hbl active at 1f h ; note 13 14.4 14.7 15.0 m s at 2f h ; note 13 7.2 7.35 7.5 m s cr bl control range of the black current stabilization notes 15 and 16 - 1 - v v blank blanking voltage level difference with black level; note 11 - 0.4 - 0.5 - 0.6 v v blank(leak) blanking voltage level during leakage measurement -- 0.1 - v v blank(l) blanking voltage level during low measuring pulse - 0.25 - v v blank(h) blanking voltage level during high measuring pulse - 0.38 - v d v (rgb)(mp) adjustment range of the ratio between the amplitudes of the rgb drive voltage and the measuring pulses note 11 - 6 - db v bl(wbc) black level at the output at which bit wbc is set to 1 nominal value 2.4 2.5 2.6 v window; note 16 - 100 - mv d bl/ d t variation of black level with temperature note 5 - 1.0 - mv/k cr bl black level offset adjustment range on red and green channels 15 steps; 10 mv/step 70 75 80 mv symbol parameter conditions min. typ. max. unit
2000 may 08 21 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series d v bl relative variation in black level between the three channels during variations of note 5 supply voltage ( 10%) nominal controls -- 20 mv saturation (50 db) nominal contrast -- 20 mv contrast (20 db) nominal saturation -- 20 mv brightness ( 0.5 v) nominal controls -- 20 mv temperature (range 40 c) -- 20 mv s/n signal-to-noise ratio of the output signals notes 5 and 17 60 -- db b o(y)(10pf) luminance bandwidth of output signals with 10pf load capacitance; note 12 rgb-1 input; at - 3db 22 25 - mhz rgb-2 input; at - 3db 29 33 - mhz luminance input; at - 3db 23 26 - mhz b o(y)(25pf) luminance bandwidth of output signals with 25pf load capacitance rgb-1 input; at - 3db 20 23 - mhz rgb-2 input; at - 3db 23 26 - mhz luminance input; at - 3db 21 24 - mhz w hite - point adjustment i 2 c nom i 2 c-bus setting for nominal gain - 32 dec - d g rgb adjustment range of rgb drive levels cl control bits; see ta b l e 1 5 3.2 3.6 4.0 db d g v gain control range to compensate spreads in picture tube characteristics white point controls - 3 - db 2- point black current stabilization ; input pin 44; note 18 i ref(l) amplitude of low reference current - 8 -m a i ref(h) amplitude of high reference current - 20 -m a i l acceptable leakage current - 100 -m a v iref voltage on measurement pin pin 44; loop closed 3.15 3.3 3.45 v i scan(max) maximum current during scan pin 44; loop open circuit note 18 -- - symbol parameter conditions min. typ. max. unit
2000 may 08 22 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series b eam current limiting ; input pin 43 v bias internal bias voltage 3.5 3.6 3.7 v v cr contrast reduction starting voltage 3.1 3.3 3.5 v v dif(cr) voltage difference for full contrast reduction 2.0 2.2 2.4 v v bri brightness reduction starting voltage 1.6 1.8 2.0 v v dif(br) voltage difference for full brightness reduction - 1 - v i ch(int) internal charge current 1.5 2.0 2.5 m a i dch(max) maximum discharge current when the pwl is active 3.5 4.0 4.5 ma p eak white limiter ; note 19 i ch(pwl) charge current pwl ?lter pin pin 34; 1f v mode 13 16 19 m a pin 34; 2f v mode 26 32 38 m a i dch(pwl) discharge current pwl ?lter pin pin 34; 1f v mode 52 64 76 m a pin 34; 2f v mode 100 120 140 m a v i(y)(b-w) y-input signal amplitude at which peak white limiter is activated (black-to-white value) pwl range, 15 steps; at maximum contrast 0.65 - 1.0 v v o(rgb)(b-w) rgb output signal amplitude at which peak white limiter is activated (black-to-white value) pwl range, 15 steps; nominal setting of white point controls; note 20 2.2 - 3.4 v s oft clipper ; note 21 d g v(sc) soft clipper gain reduction at maximum contrast; see fig.9 - 15 - db v o(clip-pwl) output level compared to pwl for 100 ire peak signal (a+b)/a; see fig.9 - 118 - % blue stretch ; note 22 d g rg decrease of small signal gain for red and green channels - 17 - % f ixed beam current switch - off ; notes 23, 24 and 25 v fbcso detection level 1 1.5 2 v v i(fbcso)(max) maximum input voltage -- 5.5 v i dch discharge current when the ?xed beam current function is activated sink current pin 44; note 26 0.85 1.0 1.15 ma v o(max) maximum output voltage at the rgb outputs 2-point stabilization; note 26 - 6.0 - v 1-point stabilization; note 26 - 5.6 - v t dch discharge time of picture tube when switching to standby tfbc = 0; see fig.15 - 18.6 - ms tfbc = 1; see fig.15 - 25 - ms symbol parameter conditions min. typ. max. unit
2000 may 08 23 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series horizontal synchronization and de?ection h d input signal ; pin 24 v il low-level of input voltage note 27 -- 0.8 v v ih high-level of input voltage note 27 2.0 - 5.5 v i i(hd) input current - 10 - +10 m a t r(hd) rise time -- 100 ns t f(hd) fall time -- 100 ns t w(hd) pulse width 200 ns - 1/4 line i nternal reference signal ; crystal or resonator connected to pins 20 and 21; note 28 f xtal resonator frequency - 12 - mhz r s(xtal) resonator series resistance c l =60pf -- 30 w v i(stab)(p-p) stabilized input signal (peak-to-peak value) 0.5 0.8 1.0 v g m(max) maximum transconductance 4 5 - ma/v z i input impedance 50 -- k w c i input capacitance -- 10 pf c o output capacitance -- 5pf e xternal reference signal ; input pin 20 f xtali input signal frequency - 12 - mhz v i(xtali)(p-p) input signal amplitude (peak-to-peak value) ac coupled 0.8 - 2v f irst control loop ; note 29 f o(nom) free-running frequency 1f h mode; note 30 - 15.65 - khz 2f h mode; note 30 - 31.3 - khz 2f h mode; hdtv = 1; note 30 - 33.7 - khz d f nom tolerance on free-running frequency note 30 -- 1% f h/cr holding/catching range of pll 1f h mode 0.75 0.8 0.85 khz 2f h mode 1.5 1.6 1.7 khz d t line maximum line time difference per line 1f h mode - 2 - +2 m s 2f h mode - 1 - +1 m s f contr frequency control range in multi-sync mode 1f h mode 15 - 25 khz 2f h mode 30 - 50 khz d f corr maximum speed of frequency correction in multi-sync mode -- 100 khz/s v hsel voltage on pin hsel 1f h mode 0 - 1v 2f h mode; pin must be left open circuit 4 5 5.5 v symbol parameter conditions min. typ. max. unit
2000 may 08 24 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series s econd control loop ; pin 14 dj i / dj o control sensitivity (loop gain) d t i / d t 0 500 --m s/ m s k cor correction factor k note 31 - 0.5 - t contr control range from start of horizontal output to mid ?yback 1f h mode; note 32 0 - 23.6 m s 2f h mode; note 32 0 - 11.8 m s t h(shift) horizontal shift range 1f h mode; 63 steps - 4.5 -m s 2f h mode; 63 steps - 2.25 -m s dj control sensitivity for dynamic phase compensation 1f h mode - 0.4 -m s/v 2f h mode - 0.2 -m s/v v i(dp)(comp) input voltage range for dynamic phase compensation pin 14; note 33 1.5 4 6.5 v z i input impedance pin 14; note 33 100 k w t par(cor)(max) maximum range of parallelogram correction 1f h mode; end of ?eld; ?yback width 11 m s; note 34 0.48 0.54 0.60 m s 2f h mode; end of ?eld; ?yback width 5.5 m s; note 34 0.24 0.27 0.30 m s t bow(cor)(max) maximum range of bow correction 1f h mode; end of ?eld; ?yback width 11 m s; note 34 0.48 0.54 0.60 m s 2f h mode; end of ?eld; ?yback width 5.5 m s; note 34 0.24 0.27 0.30 m s h orizontal flyback input ; pin 13 v sw(hblnk) switching level for horizontal blanking 0.2 0.3 0.4 v v sw(p2) switching level for phase detection 3.8 4.0 4.2 v v i(hfb)(max) maximum input voltage -- v p v z i input impedance 10 -- m w h orizontal output ; pin 8, open collector ; note 35 v ol low-level output voltage i o =10ma -- 0.3 v i o(hor) maximum allowed output current -- 10 ma v o(max) maximum allowed output voltage -- v p v d duty factor v o = low (t on ) 51.6 51.8 52.0 % t on switch-on time of horizontal drive pulse tv mode, hdtv = 0, ess = 0 155 159 163 ms t off switch-off time of horizontal drive pulse tv mode, hdtv = 0, ess = 0 48 50 52 ms t on(ess) switch-on time for extended slow start tv mode, hdtv = 0, ess = 1 1150 1175 1200 ms symbol parameter conditions min. typ. max. unit
2000 may 08 25 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series d t jitter ( s )1f h mode; note 36 - 1.4 - ns 2f h mode; note 36 - 1.0 - ns s andcastle output ; pin 9; note 37 v sco(0) zero level 0 0.5 1.0 v i sink sink current 0.5 0.7 0.9 ma v o(sco) output voltage during clamp pulse 4.2 4.5 4.8 v during blanking 2.3 2.5 2.7 v i source source current 0.5 0.7 0.9 ma i i(grd) guard pulse input current required to stop the blanking after a vertical blanking period note 38 1.0 - 3.5 ma t w(1) pulse width in 1f h mode clamp pulse, 22 llc pulses - 3.2 -m s vertical blanking (50/60 hz) - 22/17 - lines t w(2) pulse width in 2f h mode clamp pulse, 22 llc pulses - 1.6 -m s clamp pulse, hdtv = 1, hdcl = 1, 18 llc; see fig.11 - 1.22 -m s vertical blanking; depends on vwait setting; see fig.13 -- t d(bk-hd) delay between start h d pulse and start of clamp pulse 1f h mode, 37 llc pulses - 5.4 -m s 2f h mode, 37 llc pulses - 2.7 -m s 2f h mode, hdcl = 1, 14 llc pulses, see fig.11 - 0.94 -m s vertical synchronization and geometry processing v d input signal ; pin 23 v il low-level of input voltage -- 0.8 v v ih high-level of input voltage 2.0 - 5.5 v i i(vd) input current - 10 - +10 m a t r(vd) rise time -- 100 ns t f(vd) fall time -- 100 ns t w(vd) pulse width 0.5 - 63.5 lines v ertical divider and ramp generator ; pins 15 and 16; note 39 n h number of lines per ?eld (vga mode is valid only for tda9331h and tda9332h) 1f h tv mode 244 - 511.5 lines 1f h vga mode 175 - 450 lines 2f h ; 2f v ; tv mode 244 - 511.5 lines 2f h ; 1f v ; tv mode 488 - 1023.5 lines 2f h vga mode 350 - 900 lines symbol parameter conditions min. typ. max. unit
2000 may 08 26 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series n h(nom) divider value when not locked (number of lines per ?eld) (vga mode is valid only for tda9331h and tda9332h) 1f h or 2f h ; 2f v ; tv mode; vff = 0 - 312.5 - lines 1f h or 2f h ; 2f v ; tv mode; vff = 1 - 262.5 - lines 2f h ; 1f v ; tv mode; vff = 0 - 625 - lines 2f h ; 1f v ; tv mode; vff = 1 - 525 - lines 1f h ; vga mode - 288 - lines 2f h ; vga mode - 576 - lines v saw(p-p) sawtooth amplitude (peak-to-peak value) vs = 1fh; c = 100 nf; r = 39 k w - 3.0 - v i dch discharge current - 1.2 - ma i ch(ext)(r) charge current set by external resistor r = 39 k w ; vs = 1fh; svf=0 - 16 -m a r = 39 k w ; vs = 1fh; svf=1 - 32 -m a slope vert vertical slope control range (63 steps) - 20 - +20 % d i ch charge current increase 60/50 hz or 120/100 hz 18.0 19.0 20.0 % v rampl low-voltage level of ramp - 2.3 - v v ertical drive outputs ; pins 1 and 2 i o(ver)(p-p) differential output current (peak-to-peak value) va = 1fh 0.88 0.95 1.02 ma i cm common mode current 360 400 440 m a v o(vdo) output voltage range 0 - 4.0 v lin vert vertical linearity upper/lower ratio; note 40 0.99 1.01 1.03 d e - interlace d 1st?d ?rst ?eld delay dip = 0; note 41 - 0.5h - e-w width ; note 42 cr control range 63 steps 100 - 65 % i o(eq) equivalent output current vga = 0; note 42 0 - 700 m a v o(ew) e-w output voltage range 1.0 - 8.0 v i o(ew) e-w output current range 0 - 1200 m a e-w parabola / width cr control range 63 steps 0 - 22 % i o(eq) equivalent output current e-w = 3fh 0 - 440 m a e-w corner / parabola cr control range 63 steps - 43 - 0% i o(eq) equivalent output current pw = 3fh; e-w = 3fh - 190 - 0 m a e-w trapezium cr control range 63 steps - 5 - +5 % i o(eq) equivalent output current - 100 - +100 m a symbol parameter conditions min. typ. max. unit
2000 may 08 27 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series e-w eht tracking v i(ehtin) input voltage 1.2 - 2.8 v m scan scan modulation range - 7 - +7 % j ew sensitivity 63 steps 0 - 9 %/v v ertical amplitude cr control range 63 steps; sc = 00h 80 - 120 % i o(eq)(diff)(p-p) equivalent differential vertical drive output current (peak-to-peak value) sc = 00h 760 - 1140 m a v ertical shift cr control range 63 steps - 5 - +5 % i o(eq)(diff)(p-p) equivalent differential vertical drive output current (peak-to-peak value) - 50 - +50 m a s- correction cr control range 63 steps 0 - 30 % v ertical eht tracking / overvoltage protection v i input voltage 1.2 - 2.8 v m scan scan modulation range 4.5 5 5.5 % j vert vertical sensitivity 5.7 6.3 6.9 %/v i o(eq)(ew) ew equivalent output current +100 -- 100 m a v ov(det) overvoltage detection level note 43 3.7 3.9 4.1 v v ertical zoom mode ( output current variation with respect to nominal scan ); note 44 f zoom vertical zoom factor 63 steps 0.75 - 1.38 f lim output current limiting and rgb blanking 1.01 1.05 1.08 v ertical scroll ; note 45 cr control range (percentage of nominal picture amplitude) 63 steps - 18 - +19 % v ertical wait ; note 46 t d(scan) delay of start vertical scan 23 steps 8 - 31 lines f lash detection input ; pin 5; note 43 v i(flash) input voltage range 0 - v p v v flash(det) voltage detection level - 2 - v v det(hys) detection level hysteresis - 0.2 - v t w(flash) pulse width 200 -- ns symbol parameter conditions min. typ. max. unit
2000 may 08 28 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series notes 1. the normal operation of the ic is guaranteed for a supply voltage between 7.2 and 8.8 v. when the supply voltage drops below the por level, status bit por is set and the horizontal output is switched off. when the supply voltage is between 7.2 v and the por level, the horizontal frequency is kept in the specified holding range. 2. for the low power start-up mode, a voltage of 5 v has to be supplied to pin 22. the current that is required for this function is about 3.0 ma. after the start-up voltage is applied, the signal at the horizontal drive output will have nominal t off , while t on grows gradually from zero to about 30% of the nominal value, resulting in a line frequency of approximately 50 khz (2fh) or 25 khz (1fh). the start-up mode is continued as soon as the main supply voltage is switched on and the i 2 c-bus data has been received. after status bit por has been read out, bits stb must be set to 1 within 24 ms, to continue slow start. if bits stb are not sent within 24 ms, the horizontal output will be automatically switched off via slow stop. it is also possible to first set bits stb to 1, before reading bit por. start-up of the horizontal output will then continue 24 ms after bit por is read. when the main supply is present, the 5 v supply on pin 22 can be removed. if low power start-up is not used, pin 22 should be connected to ground. more information can be found in the application report. 3. the rgb to yuv matrix on the rgb-1 input is the inverse of the yuv to rgb matrix for pal. for a one-on-one transfer of all three channels from the rgb-1 input to the rgb output, the pal colour difference matrix should be selected (mat = 0, mus = 0). 4. the colorimetry that is used for high definition atsc signals is described in document ansi/smpte 274m-1995. the formula to compute the luminance signal from the rgb primary components differs from the formula that is used for the pal system. the consequence is that a different matrix is needed to calculate the internal g - y signal from the r - y and b - y signals, see the formulas below: the g - y signal can be derived from the formula for y: i 2 c-bus control inputs/outputs; pins 10 and 11 v il low-level input voltage -- 1.5 v v ih high-level input voltage 3.5 - 5.5 v i il low-level input current v il =0v - 0 -m a i ih high-level input current v ih = 5.5 v - 0 -m a v ol low-level output voltage sda; i ol =6ma -- 0.6 v dac output ; pin 25; note 47 v o(min) minimum output voltage 0.15 0.3 0.4 v v o(max) maximum output voltage 3.7 4.0 4.3 z o output impedance note 47 0.3 - 10 k w i o output current -- 2ma symbol parameter conditions min. typ. max. unit y 0.2126r 0.7152g 0.0722b ++ = ry C 0.7874r 0.7152g C 0.0722b 1.575 maximum amplitude () C = by C 0.2126r C 0.7152g C 0.9278b 1.856 maximum amplitude () + = gy C 0.2973 C ry C () 0.1010 b y C () C =
2000 may 08 29 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series atsc signals are transmitted as yp b p r signals. the colour-difference components p b and p r are amplitude corrected versions of b - y and r - y: note that the yuv input of the tda933xh is actually a y, - (r - y) and - (b - y) input. when the tv set has an input for a ypbpr signal with amplitudes of 0.7 v for all three components, the signals should be amplified to y, - (b - y) and - (r - y) signals as follows: 5. this parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 6. the inputs for rgb-1 and rgb-2 insertion (pins 33 and 38) both supply a small source current to the pins. if the pins are left open circuit, the input voltage will rise above the insertion switching level. 7. this parameter is measured at nominal settings of the various controls. 8. the switching of the osd (rgb-2) input has two modes, which can be selected via the i 2 c-bus: a) fast switching between the osd signal and the internal rgb signals. b) blending (fading) function between the osd signal and the internal rgb signals. the blending control curve is given in fig.4. the blender input is optimized for the blender output of the saa5800 (artistic). 9. the saturation, contrast and brightness controls are active on the yuv signals and on the first rgb input signals. nominal contrast is specified with the contrast dac in position 32 dec, nominal saturation with the saturation dac in position 22 dec. the second rgb input (which is intended to be used for osd and teletext display) can only be controlled on brightness. 10. for video signals with a black level that deviates from the back-porch blanking level, the signal is stretched to the blanking level. the amount of correction depends on the ire value of the signal (see fig.8). the black level is detected by means of an internal capacitor. the black level stretcher can be switched on and off via bit bks in the i 2 c-bus. the values given in the specification are valid only when the luminance input signal has an amplitude of 1 v (b-w). 11. because of the 2-point black current stabilization circuit, both the black level and the amplitude of the rgb output signals depend on the drive characteristic of the picture tube. the system checks whether the returning measuring currents meet the requirement and adapts the output level and gain of the circuit as necessary. therefore, the typical values of the black level and amplitude at the output are just given as an indication for the design of the rgb output stage. a) the 2-point black level system adapts the drive voltage for each cathode such that the two measuring currents have the right value. the consequence is that a change in the gain of the output stage will be compensated by a gain change of the rgb control circuit. because different picture tubes may require different drive voltage amplitudes, the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the i 2 c-bus. this is indicated in the parameter adjustment range of rgb drive levels. b) because of the dependence of the output signal amplitude on the application, the peak-white and soft-clipping limiting levels have been related to the input signal amplitude. p b 0.5 b y C () 1 0.0722 C --------------------------- by C () 1.856 ------------------ == p r 0.5 r y C () 1 0.2126 C --------------------------- - ry C () 1.575 ------------------ - == y in,ic 1 0.7 ------- - y in,tv 1.43y in,tv == by C () C in,ic 1.856 0.7 -------------- - p bin tv , 2.65 C p b in,tv == ry C () C in,ic 1.575 0.7 -------------- - p rin tv , 2.25 C p r in,tv ==
2000 may 08 30 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series c) the signal amplitude at the rgb outputs of the tda933xh depends on the gain of the rgb amplifiers. the gain of the rgb amplifiers should be 35 to get the nominal signal amplitude of 2 v (b-w) at the rgb outputs for a cathode drive level of 70 v (b-w) and the nominal setting of the drive level bits (cl 3210 = 1000, see table 15). 12. the bandwidth of the video channels depends on the capacitive load at the rgb outputs. for 2f h or vga applications, external (pnp) emitter followers on the rgb outputs of the tda933xh are required, to avoid reduction of the bandwidth by the capacitance of the wiring between the tda933xh and the rgb power amplifiers on the picture tube panel. if emitter followers are used, it should be possible to obtain the bandwidth figures that are mentioned for 10 pf load capacitance. 13. the timing of the horizontal blanking pulse on the rgb outputs is illustrated in fig.10. a) the start of the blanking pulse is determined by an internal counter blanking that starts 40 llc (line locked clock) pulses before the centre of the horizontal flyback pulse. this is 5.8 m s for 1fh and 2.9 m s for 2fh tv mode. the end of the blanking is determined by the trailing edge of the flyback pulse. if required, the start of the counter blanking can be adjusted in 15 steps with bus bits lbl3 to lbl0. this can be useful when hdtv or vga signals are applied to the ic. b) when the reproduction of 4 : 3 pictures on a 1 6 : 9 picture tube is realized by reducing the horizontal scan amplitude, the edges of the picture may be slightly disturbed. this effect can be prevented by adding an additional blanking pulse to the rgb signals. this blanking pulse is derived from the horizontal oscillator and is directly related to the incoming h d pulse (independent of the flyback pulse). the additional blanking pulse overlaps the normal blanking signal by approximately 1 m s (1f h ) or 0.5 m s (2f h ) on both sides. this wide blanking is activated by bit hbl. the phase of this blanking can be controlled in 15 steps by bits hb3 to hb0. 14. when a yuv or rgb signal is applied to the ic and no separate horizontal or vertical timing pulses are available, an external sync separator circuit is needed. the tda933xh has an edge triggered phase detector circuit on the h d input that uses the start of the h d pulse as timing reference. to avoid horizontal phase disturbances during the vertical blanking period, it is important that the sync separator does not generate extra horizontal sync pulses during the vertical sync pulse on the video signal. 15. start-up behaviour of the ccc loop. after the horizontal output is released via bits stb, the rgb outputs are blanked and the ccc loop is activated. because the picture tube is cold, the measured cathode currents are too small, and both gain and offset are set at the maximum value so that the ccc loop gets out of range and status bit bcf is set to 1. once the picture tube is warm, the loop comes within range and the set signal for bit bcf is removed. status bit bcf is set if the voltage of at least one of the cut-off measurement lines at the rgb outputs is lower than 1.5 v or higher than 3.5 v. the rgb outputs are unblanked as soon as bit bcf changes from 1 to 0. to avoid a bright picture after switch-on with a warm picture tube, reset of bit bcf is disabled for 0.5 s after switch-on of the horizontal output. if required, the blanking period of the rgb outputs can be increased by forcing the blanking level at the rgb outputs via rbl = 1. when status bit bcf changes from 1 to 0, bit rbl can be set to 0 after a certain waiting period. 16. voltage v g2 of the picture tube can be aligned with the help of status bits wbc and hbc. bit wbc becomes 1 if the lowest of the three rgb output voltages during the cut-off measurement lines is within the alignment window of 0.1 v around 2.5 v. bit hbc is 0 if the lowest cut-off level is below 2.6 v, and 1 if this level is above 2.6 v. a) voltage v g2 should be aligned such that bit wbc becomes 1. if bit wbc is 0, bit hbc indicates in which direction voltage v g2 should be adjusted. if bit hbc = 0, the dc level at the rgb outputs of the ic is too low and voltage v g2 should be adjusted lower until bit wbc becomes 1. if hbc = 1, the dc level is too high and voltage v g2 should be adjusted higher until bit wbc becomes 1. b) it should be noted that bit wbc is only meant for factory alignment of voltage v g2 . if the value of bit wbc depends on the video content, this is not a problem. correct operation of the black current loop is guaranteed as long as status bit bcf = 0, meaning that the dc level of the measurement lines at the rgb outputs of the ic is between 1.5 and 3.5 v. 17. signal-to-noise ratio (s/n) is specified as a peak-to-peak signal with respect to rms noise (bandwidth 10 mhz). 18. this is a current input. when the black current feedback loop is closed (only during measurement lines or during fixed beam current switch off), the voltage at this pin is clamped at 3.3 v. when the loop is open circuit, the input is not
2000 may 08 31 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series clamped and the maximum sink current is approximately 100 m a. the voltage on the pin must not exceed the supply voltage. 19. the control circuit contains a pwl circuit and a soft clipper. a) the detection level of the pwl can be adjusted via the i 2 c-bus in a control range between 0.65 and 1.0 v (b-w). this amplitude is related to the y input signal, typical amplitude 1 v (b-w), at maximum contrast setting. the detector measures the amplitude of the rgb signals after the contrast control. the output signal of the pwl detector is filtered by an external capacitor, so that short transients in the video signal do not activate the limiting action. because the capacitor is externally available at pin 34, the set maker can adapt the filter time constant as required. the contrast reduction of the pwl is obtained by discharging the external capacitor at the beam current limiting input (pin 43). to avoid the pwl circuit from reducing the contrast of the main picture when the amplitude of the inserted rgb2 signal is too high, the output current of the pwl detector is disabled when the fast blanking input (pin 38) is high. in blending mode (obl = 1), the pwl detector is disabled when the blending voltage is above the 50% insertion level. the soft clipper circuit will still limit the peak voltage at the rgb outputs. b) in addition to the pwl circuit, the ic contains a soft clipper function which limits short transients that exceed the pwl. the difference between the pwl and the soft clipping level can be adjusted between 0 and 10% in three steps via the i 2 c-bus, with bus bits sc1 and sc0 (soft clipping level equal or higher than the pwl). it is also possible to switch off the soft clipping function. 20. the above-mentioned output amplitude range at which the pwl detector is activated is valid for nominal settings of the white point controls, and when the ccc loop is switched off or set to 1-point stabilization mode. in 2-point stabilization mode, the mentioned range is only valid when the gain of the rgb output stages is dimensioned such that the rgb output amplitudes are 2 v (b-w) for nominal contrast setting, see also note 11. 21. the soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 1 v (b-w) at the luminance input. to prevent the beam current limiter from operating, a dc voltage of 3.5 v must be applied to pin 43. the contrast is set at the maximum value, the pwl at the minimum value, and the soft clipping level is set at 0% above the pwl (sc 10 = 00). the tangents of the sawtooth waveform at one of the rgb outputs is now determined at the beginning and end of the sawtooth. the soft clipper gain reduction is defined as the ratio of the slopes of the tangents for black and white, see fig.9. 22. when the blue stretch function is activated (via i 2 c-bus bit bls), the gain of the red and green channels is reduced for input signals that exceed a value of 80% of the nominal amplitude. the result is that the white point is shifted to a higher colour temperature. 23. switch-off behaviour of tda933xh. for applications with an eht generator without bleeder resistor, the picture tube capacitance can be discharged with a fixed beam current when the set is switched off. the magnitude of the discharge current is controlled via the black current loop. the fixed beam current mode can be activated with bit fbc. with the fixed beam current option activated, it is still possible to have a black screen during switch-off. this is realized by placing the vertical deflection in the overscan position. this mode is activated by bit oso. there are two possible situations for switch-off (see notes 24 and 25). 24. the set is switched to standby via the i 2 c-bus. in this situation, the procedure is as follows: a) vertical scan is completed. b) vertical flyback is completed. c) slow stop of the horizontal output is started, by gradually reducing the on-time at the horizontal output from nominal to zero. d) at the same moment, the fixed beam current is forced via the black current loop (if fbc = 1). e) if oso = 1, the vertical deflection stays in overscan position; if oso = 0, the vertical deflection keeps running. f) the slow stop time is approximately 50 ms, the fixed beam current flows for 18.6 ms or 25 ms, depending on the value of bit tfbc, see fig.15. 25. the set is switched off via the mains power switch. when the mains supply is switched off, the supply voltage of the line deflection circuit of the tv set will decrease. a detection circuit must be made that monitors this supply voltage.
2000 may 08 32 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series when the supply voltage suddenly decreases, pin fbcso (fixed beam current switch-off) of the tda933xh must be pulled high. in this situation, the procedure is as follows: a) vertical scan is completed. b) vertical flyback is completed. c) the fixed beam current is forced via the black current loop (if fbc = 1). the horizontal output keeps running. as the supply voltage for the line transformer decreases, the eht voltage will also decrease. d) if oso = 1, the vertical deflection stays in overscan position; if oso = 0, the vertical deflection keeps running. e) when the supply voltage of the tda933xh drops below the por level, horizontal output and fixed beam current are stopped. 26. the discharge current for the picture tube can be increased with an external current division circuit on the black current input (pin 44). the current division should only be active for high cathode currents, so that the operation of the black current stabilization loop is not affected. when the feedback current supplied to pin 44 is less than 1ma, the dc level at the rgb outputs will go to the maximum value of 6.0 v (2-point black current stabilization) or 5.6 v (1-point or no black current stabilization). 27. a stable switching of the h d input is realized by using a schmitt trigger input. 28. the simplified circuit diagram of the oscillator is given in fig.3. to ensure that the oscillator will start-up, the ceramic resonator must fulfil the following condition: . example: when the resonator is loaded with 60 pf (this is a typical value for a 12 mhz resonator), the series resistance of the resonator must be smaller than 30 w . a suitable ceramic resonator for use with the tda933xh is the murata cst12.0mt, which has built-in load capacitances c a and c b . for higher accuracy, it is also possible to use a quartz crystal, which is even less critical with respect to start-up because of its lower load capacitance. 29. pin hsel must be connected to ground in a 1f h application; it must be left open circuit for a 2f h application. the tda9331h and tda9332h can be switched to a multi-sync mode, in which the horizontal frequency can vary between 15 and 25 khz (1f h mode) or 30 and 50 khz (2f h mode). 30. the indicated tolerance on the free-running frequency is only valid when an accurate reference frequency (obtained with an accurate 12 mhz crystal) is used. the tolerance of the reference resonator must be added to obtain the real tolerance on the free-running frequency. 31. the correction factor k of the phase-2 loop is defined as the amount of correction per line period of a phase error between the horizontal flyback pulse and the internal phase-2 reference pulse. when k = 0.5, the phase error between the flyback pulse and the internal reference is halved each line period. 32. the control range of the second control loop depends on the line frequency. the maximum control range from the rising edge of hout to the centre of the flyback pulse is always 37% of one line period, for the centre position of the dynamic phase compensation (4.0 v at pin 14). 33. the dynamic phase compensation input (pin 14) is connected to an internal reference voltage of 4.0 v via a resistor of 100 k w . if dynamic phase compensation is not used, this pin should be decoupled to ground (pin 19) via a capacitor of 100 nf. 34. the range of parallelogram and bow correction is proportional to the width of the horizontal flyback pulse. for zero correction, use dac setting 7 dec or 0111 (bin). the effect of the corrections is shown in fig.16. 35. for safe operation of the horizontal output transistor and to obtain a controlled switch-on time of the eht, the horizontal drive starts up in a slow start mode. the horizontal drive starts with a very short on-time of the horizontal output transistor (line locked clock pulse, i.e. 72 ns), the off-time of the transistor is identical to the off-time in normal operation. the starting frequency during switch-on is therefore approximately twice the normal value. the t on is slowly increased to the nominal value in approximately 160 ms (see fig.15). when the nominal frequency is reached, the pll is closed such that only very small phase corrections are necessary. this ensures safe operation of the output stage. c l 2 r i 1.1 10 19 C
2000 may 08 33 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series a) for picture tubes with dynamic astigmatic focusing (daf) guns, the rise of the eht voltage between 75 and 100% is preferred to be even slower than the rise time from 0 to 75%. this can be realized by activating bit ess, at which the total switch-on time of the horizontal output pulse is approximately 1175 ms. b) during switch-off, the slow-stop function is active. this is realized by decreasing the t on of the output transistor complementary to the start-up behaviour. the switch-off time is approximately 50 ms. the slow-stop procedure is synchronized to the start of the first new vertical field after reception of the switch-off command. during the slow-stop period, the fixed beam current switch-off can be activated (see also note 23). this current is active during a part of the slow stop period, see fig.15. c) the horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback pulse. this protection is not active during the switch-on or switch-off period. 36. this parameter is not tested during production and is just given as application information for the designer of the television receiver. 37. the rise and fall times of the blanking pulse and clamping pulse at the sandcastle output (pin 9) depend on the capacitive load. the value of the source current during the rising edge or sink current during the falling edge is 0.7 ma (typical value). 38. the vertical guard pulse from the vertical output stage should fall within the vertical blanking period (see figs 12 and 13) and should have a width of at least one line period. for the detection of a missing pulse, a guard current value of 1 ma during normal operation is sufficient. if the rgb outputs must also be blanked if the guard pulse lasts longer than the vertical blanking period, the guard current must have a value between 2.6 ma and 3.5 ma. 39. switching between the 1f v or the 2f v mode is realized via bit svf. 40. the vertical linearity is measured on the differential output current at the vertical drive output (pins 1 and 2) for zero s-correction. the linearity is defined as the ratio of the upper and lower half amplitudes at the vertical output. the upper amplitude is measured between lines 27 and 167, the lower amplitude between lines 167 and 307 for a 50 hz video signal. 41. the field detection mechanism is explained in fig.17. a) the incoming v d pulse is synchronized with the internal clock signal ck2h that is locked to the incoming h d pulse. if the synchronized v d pulse of a field coincides with the internally generated horizontal blanking signal hblnk, then this is field 1. if the synchronized v d pulse does not coincide with hblnk, then this is field 2. signals ck2h and hblnk are both output signals of the horizontal divider circuit that is part of the line-locked clock generator. a reliable field detection is important for correct interlacing and de-interlacing and for the correct timing of the measurement lines of the black current loop. for the best noise margin, the edges of the v d pulse should be on approximately 1 4 and 3 4 of the line, referred to the rising edges of the h d input signal. b) if bus bit vsr = 0, the end of the v d pulse is used as reference for both field detection and start of vertical scan. if vsr = 1, the starting edge is used. 42. output range percentages mentioned for e-w control parameters are based on the assumption that the e-w modulator is dimensioned such that 400 m a variation in e-w output current of the ic is equivalent to 20% variation in picture width. in vga mode, the e-w output current is proportional to the applied line frequency. 43. the ic has protection inputs for flash protection and overvoltage protection. a) the flash protection input is used to switch the horizontal drive output off immediately if a picture tube flashover occurs, to protect the line output transistor. an external flash detection circuit is needed. when the flash input is pulled high, the horizontal output is switched off and status bit fls is set. when the input turns low again, the horizontal output is switched on immediately without i 2 c-bus intervention via the slow start procedure. b) the overvoltage (x-ray) protection is combined with the eht compensation input. when this protection is activated, the horizontal drive can be directly switched off (via the slow stop procedure). it is also possible to continue the horizontal drive and only set status bit xpr in output byte 01 of the i 2 c-bus. the choice between the two modes of operation is made via bit prd. 44. the ics have a zoom adjustment possibility for the horizontal and vertical deflection. for this reason, an extra dac is included in the vertical amplitude control, which controls the vertical scan amplitude between 0.75 and 1.38 of the
2000 may 08 34 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series nominal scan. at an amplitude of 1.05 times the nominal scan, the output current is limited and the blanking of the rgb outputs is activated, see fig.14. in addition to the variation of the vertical amplitude, the picture can be vertically shifted on the screen via the scroll function. the nominal scan height must be adjusted at a position of 19h (25 dec) of the vertical zoom dac and 1fh (31 dec) for the vertical scroll dac. 45. the vertical scroll function is active only in the expand mode of the vertical zoom, i.e. at a dac position larger than 10h (16 dec). 46. with the vertical wait function, the start of the vertical scan can be delayed with respect to the incoming vertical sync pulse. the operation is different for the various scan modes, see table 54 and figs 12 and 13. the minimum value for the vertical wait is 8 line periods. if the setting is lower than 8, the wait period will remain 8 line periods. 47. in the TDA9330h and tda9332h, the dac output is i 2 c-bus controlled. in the tda9331h, the dac output voltage is proportional to the centre frequency of the line-oscillator. in tv mode, the output voltage will always be at the minimum value. in vga mode, the output is at the minimum value for the lowest centre frequency (32 khz) and at the maximum value for the highest centre frequency (48 khz). the output impedance of the dac output depends on the output voltage. the output consists of an emitter follower with an internal resistor of 50 k w to ground. table 54 operation of the vertical wait function mode start of vertical scan 1f h ; tv mode ?xed; see fig.12 2f h ; tv mode; vsr = 0 end of v d plus vertical wait setting 2f h ; tv mode; vsr = 1 start of v d plus vertical wait setting 1f h ; multi sync mode start of v d plus vertical wait setting 2f h ; multi sync mode start of v d plus vertical wait setting
2000 may 08 35 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, halfpage mgr447 100 k w xtali xtalo crystal or ceramic resonator r i l i c i c i g m c p c a c b fig.3 simplified diagram of crystal oscillator. f osc 1 l i c i c l c i c l + ------------------ - 2 p ------------------------------------- = c l c p c a c b c a c b + -------------------- + = requirement for start-up: c 2 l r i 1.1 10 19 C handbook, full pagewidth 100 0 0 1.0 1.4 0.4 0.31 0.8 1.2 0.2 0.725 1.14 0.6 20 40 60 80 mgr448 v insert (v) blending (%) external internal fig.4 blending characteristic (typical curve and minimum/maximum limits).
2000 may 08 36 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, halfpage 300 100 0 200 mgs892 02040 80 60 dac (decimal value) (%) fig.5 saturation control curve. handbook, halfpage 02040 80 200 0 160 mgs893 60 120 80 40 dac (decimal value) (%) fig.6 contrast control curve. handbook, halfpage 02040 80 1 0.5 mgs894 60 0 - 0.5 - 1 dac (decimal value) (v) fig.7 brightness control curve. conditions: settings for cathode drive and white point nominal; gain of rgb amplifiers such that the amplitude at the rgb outputs is 2 v (b-w); relative to cutoff level. handbook, halfpage 0 40 80 120 100 20 - 20 60 80 0 40 mgr452 output (ire) input (ire) a a b b a-to-a: maximum black level shift. b-to-b: level shift at 15% of peak white. fig.8 i/o relation of black level stretch circuit.
2000 may 08 37 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth 0 4 2 3 1 0 20 v o(rgb)(b-w) (v) 100 mgs895 40 60 80 yin (ire) tangent clipper off clipper on pwl input level pwl output level a b fig.9 soft clipper characteristic.
2000 may 08 38 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth mgs896 h d input pulse wide blanking (if hbl = 1) horizontal flyback pulse flyback blanking counter blanking video blanking phase slicing level (4 v) blanking slicing level (0.3 v) reference phi1 reference phi2 hshift 0 to 63 llc 101 llc 40 llc (2) (1) fig.10 timing of horizontal blanking (1 line period is 440 llc pulses). 1) position of wide blanking can be adjusted with bus bits hb3 to hb0. 2) start of line blanking can be adjusted with bus bits lbl3 to lbl0.
2000 may 08 39 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth mgs897 0.75 m s 2.35 m s 2.40 m s 5.5 m s mid blank = mid flyback 37 llc = 2.67 m s 22 llc = 1.59 m s h d input hshift 2f h ntsc signal (f h = 31.47 khz) clp pulse counter blanking 0.606 m s 0.592 m s 1.993 m s 3.784 m s 50 ns mid blank = mid flyback 18 llc = 1.22 m s h d input hdtv signal (f h = 33.75 khz) clp pulse 0.592 m s 15 llc = 1.01 m s counter blanking (a) timing in 2 f h tv mode (hdtv = 0, hdcl = 0) (b) timing in hdtv mode (hdtv = 1, hdcl = 1) hshift 40 llc = 2.69 m s + 14 llc - 16 llc 40 llc = 2.89 m s + 14 llc - 16 llc fig.11 timing of clamp pulse and line blanking in 2f h tv mode and hdtv mode. video signals are shown as illustration only. all horizontal timing signals in the ic are solely related to the start of the h d pulse that is applied to the ic. all horizontal timing signals are generated with the help of the internal line locked clock (llc). one line period is always divided into 440 line locked clock pulses. time periods depicted in the figure are only valid for line frequencies mentioned.
2000 may 08 40 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series ha ndbook, full pagewidth video from hip video from hip 625 23 312 336 reset line counter 50 hz 60 hz 1st field 2nd field 1st field 2nd field h d = h a v d = v a reset vertical sawtooth reset vertical sawtooth vertical blank akb pulses h d = h a v d = v a akb pulses vertical blank internal 2f h clock h d h d v d v d vertical blank akb pulses vertical blank akb pulses internal 2f h clock lr g b lr g b lr g b lr g b mgr453 fig.12 vertical timing pulses for 1f h tv mode. this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ...
2000 may 08 41 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series h andbook, full pagewidth h d v d reset vertical sawtooth reset vertical sawtooth vertical sawtooth measure pulse vertical blank akb pulses h d v d akb pulses vertical blank internal 2f h clock h d v d vertical blank akb pulses internal 2f h clock reset line counter lr g b lr g b lr g b reset line counter = reference vwait reference vwait vwait = 18 vwait = 12 2f h tv mode (vsr = 0) 2f h vga mode 1st field 2nd field mgr454 fig.13 vertical timing pulses for 2f h tv mode and vga mode. this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ...
2000 may 08 42 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth 70 60 50 40 100% 138% 30 20 10 0 - 10 - 20 - 30 - 40 - 50 - 60 time top picture bottom picture blanking for zoom 138% t 1/2 t vertical position (%) mgl475 75% fig.14 vertical drive waveform and blanking pulse for different zoom factors.
2000 may 08 43 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth mgs898 100 50 12 slow start t (ms) t on (% of nominal value) 32 ms (1000 lines) 18 ms 57 ms 102 ms slow stop normal ess = 1 16 ms 25 ms tfbc = 0 tfbc = 1 discharge 18.6 ms fig.15 slow start behaviour of horizontal output, and slow stop behaviour and timing of picture tube discharge pulse when ic is switched to standby via i 2 c-bus. handbook, full pagewidth mgs899 0.54 m s 0.54 m s 0.54 m s 0.54 m s (a) parallelogram correction. (b) bow correction. fig.16 horizontal parallelogram and bow correction (figures for 1f h mode).
2000 may 08 44 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, full pagewidth mgs900 v d h d hblnk field 1 detection v d h d hblnk field 2 detection v d h d clk 2h clk 2h clk 2h clk 2h hblnk field 1 detection v d h d hblnk field 2 detection (a) end of v d pulse is reference (vsr = 0) (b) start of v d pulse is reference (vsr = 1) fig.17 field detection mechanism. see also chapter characteristics; note 41.
2000 may 08 45 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series test and application information handbook, full pagewidth mgr462 tda932xh feature box tda933xh ro yin y rgb-1 rgb-2 rgb-3 rgb-4 go uin u bo vdoa vdob ewo bcl blkin hfb vin v hout h d v d h a v a if cvbs-1 tuner agc av-1 cvbs-2 cvbs cvbs(pip) cvbs(txt) yc cvbs/y-3 c-3 cvbs/y-4 c-4 av-2 saw filter comb filter fig.18 application diagram.
2000 may 08 46 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, halfpage 600 400 200 0 - 200 - 400 - 600 0t time 0.5 t (3) (2) (1) mgl483 i vert ( m a) fig.19 control range of vertical amplitude. vsh = 31; sc = 0; i vert =i 2(vdob) - i 1(vdoa) . (1) va = 0. (2) va = 31. (3) va = 63. handbook, halfpage 0 i vert ( m a) t 800 400 - 400 - 800 0 time mgl484 0.5 t (3) (2) (1) fig.20 control range of vertical slope. va = 31; vhs = 31; sc = 0. (1) vs = 0. (2) vs = 31. (3) vs = 63. handbook, halfpage 600 400 200 0 - 200 - 400 - 600 0t time mgl485 i vert ( m a) 0.5 t (1) (2) (3) va = 31; sc = 0. (1) vsh = 0. (2) vsh = 31. (3) vsh = 63. fig.21 control range of vertical shift. handbook, halfpage 600 400 200 0 - 200 - 400 - 600 0t time mgl486 i vert ( m a) 0.5 t (3) (2) (1) fig.22 control range of s-correction. va = 31; vhs = 31. (1) sc = 0. (2) sc = 31. (3) sc = 63.
2000 may 08 47 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series handbook, halfpage 0 200 t time 800 400 1000 600 1200 0 mgl489 i ew ( m a) 0.5 t (3) (2) (1) fig.23 control range of e-w width. pw = 31; cp = 31. (1) ew = 0. (2) ew = 31. (3) ew = 63. handbook, halfpage 0t time 800 300 600 400 700 500 900 mgl488 i ew ( m a) 0.5 t (1) (2) (3) ew = 31; cp = 31. (1) pw = 0. (2) pw = 31. (3) pw = 63. fig.24 control range of e-w parabola/width ratio. handbook, halfpage 0t time 800 300 600 400 700 500 900 mgl487 i ew ( m a) 0.5 t (1) (2) (3) fig.25 control range of e-w corner/parabola ratio. ew = 31; pw = 63. (1) cp = 0. (2) cp = 31. (3) cp = 63. handbook, halfpage 0t time 200 800 400 1000 600 mgl490 i ew ( m a) 0.5 t (1) (2) (3) (3) (2) (1) fig.26 control range of e-w trapezium correction. ew = 31; pw = 31. (1) tc = 0. (2) tc = 31. (3) tc = 63.
2000 may 08 48 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series adjustment of geometry control parameters the deflection processor of the tda933xh offers 15 control parameters for picture alignment, as follows: for the vertical picture alignment; s-correction vertical amplitude vertical slope vertical shift vertical zoom vertical scroll vertical wait. for the horizontal picture alignment; horizontal shift horizontal parallelogram horizontal bow e-w width with extended range for the zoom function e-w parabola/width ratio e-w upper corner/parabola ratio e-w lower corner/parabola ratio e-w trapezium correction. it is important to notice that the ics are designed for use with a dc-coupled vertical deflection stage. this is why a vertical linearity alignment is not necessary (and therefore not available). for a particular combination of picture tube type, vertical output stage and e-w output stage, the required values for the settings of s-correction and e-w corner/parabola ratio must be determined. these parameters can be preset via the i 2 c-bus and do not need any additional adjustment. the rest of the parameters are preset with the mid-value of their control range, i.e. 1fh, or with the values obtained by previously-adjusted tv sets on the production line. the vertical shift control is intended to compensate offsets in the external vertical output stage or in the picture tube. it can be shown that, without compensation, these offsets will result in a certain linearity error, especially with picture tubes that need large s-correction. in 1st-order approximation, the total linearity error is proportional to the value of the offset and to the square of the s-correction that is needed. the necessity to use the vertical shift alignment depends on the expected offsets in the vertical output stage and picture tube, on the required value of the s-correction and on the demands upon vertical linearity. to adjust the vertical shift and vertical slope independently of each other, a special service blanking mode can be entered by setting bit sbl high. in this mode, the rgb outputs are blanked during the second half of the picture. there are two different methods for alignment of the picture in the vertical direction. both methods use the service blanking mode. the first method is recommended for picture tubes that have a marking for the middle of the screen. with the vertical shift control, the last line of the visible picture is positioned exactly in the middle of the screen. after this adjustment, the vertical shift should not be changed any more. the top of the picture is positioned by adjusting the vertical amplitude, and the bottom by adjusting the vertical slope. the second method is recommended for picture tubes that have no marking for the middle of the screen. for this method, a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). the beginning of the blanking is positioned exactly on the middle of the picture using the vertical slope control. the top and bottom of the picture are then positioned symmetrically with respect to the middle of the screen by adjusting the vertical amplitude and vertical shift. after this adjustment, the vertical shift has the correct setting and should not be changed any more. if the vertical shift alignment is not required, vsh should be set to its mid-value, i.e. vsh = 1fh (31 dec). the top of the picture is then positioned by adjusting the vertical amplitude and the bottom of the picture by adjusting the vertical slope. after the vertical picture alignment, the picture is positioned in the horizontal direction by adjusting the e-w width, e-w parabola/width ratio and horizontal shift. finally (if necessary), the left and right-hand sides of the picture are aligned in parallel by adjusting the e-w trapezium control. additional horizontal corrections are possible using the parallelogram and bow controls. to obtain the correct range of the vertical zoom function, the vertical geometry should be adjusted at a nominal setting of the zoom dac at position 19h (25 dec) and the vertical scroll dac at 1fh (31 dec).
2000 may 08 49 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
2000 may 08 50 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 may 08 51 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 may 08 52 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 may 08 53 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series notes
2000 may 08 54 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series notes
2000 may 08 55 philips semiconductors preliminary speci?cation i 2 c-bus controlled tv display processors tda933xh series notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753504/02/pp 56 date of release: 2000 may 08 document order number: 9397 750 06406

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